`include "ysyx_23060189_cpu.svh"

module ysyx_23060189_ImmGen(
  input wire [`ysyx_23060189_DataBus] inst,
  input wire [`ysyx_23060189_ImmSelBus] Imm_sel,
  output wire [`ysyx_23060189_DataBus] imm
);

  wire [`ysyx_23060189_DataBus] imm_I;
  wire [`ysyx_23060189_DataBus] imm_S;
  wire [`ysyx_23060189_DataBus] imm_B;
  wire [`ysyx_23060189_DataBus] imm_U;
  wire [`ysyx_23060189_DataBus] imm_J;

  assign imm_I = {{20{inst[31]}}, inst[31:20]};
  assign imm_U = {inst[31:12], 12'b0};
  assign imm_J = {{11{inst[31]}}, inst[31], inst[19:12], inst[20], inst[30:21], 1'b0};
  assign imm_S = {{20{inst[31]}}, inst[31:25], inst[11:7]};
  assign imm_B = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0};

	MuxKey #(6, `ysyx_23060189_IMM_SEL_W, `ysyx_23060189_DATA_W) Mux (imm, Imm_sel, {
		`ysyx_23060189_IMM_I, imm_I,
		`ysyx_23060189_IMM_U, imm_U,
		`ysyx_23060189_IMM_J, imm_J,
		`ysyx_23060189_IMM_S, imm_S,
		`ysyx_23060189_IMM_B, imm_B,
		`ysyx_23060189_IMM_X, 32'b0
	}); 

endmodule
